1. Technical Field
The present invention relates to a method and system for testing integrated circuit devices in general and, in particular, to a method and system for performing burn-in tests on integrated circuit devices. Still more particularly, the present invention relates to a method and system for performing non-standard insitu burn-in tests on integrated circuit devices.
2. Description of the Prior Art
It is well-known that integrated circuit (IC) devices exhibit most failures during their early life and towards the end of their useful life. Because these early-life failures can be accelerated by increased temperature, IC devices are commonly subjected to a stress test known as a "burn-in" test in order to eliminate those IC devices that are weak or marginal.
Typically, a burn-in test requires each IC device under test to be exercised in a high-temperature and high-voltage condition. This is because high-temperature and high-voltage separately accelerate different reliability factors of an IC device. A burn-in test is effective only if a vast majority of internal nodes of each IC device under test is being toggled, and there is a robust mixture of charge potential among internal nodes of the IC device under test during the high-temperature and high-voltage conditions. This testing methodology has been traditionally accomplished by utilizing a burn-in method known as "insitu burn-in." During an insitu burn-in test, test patterns are applied to each IC device throughout a test interval, and the output of the IC device under test is also measured throughout this test period to determine its validity. An IC device is considered as "pass" only if it is fully functional during the entire test interval.
Although the traditional insitu burn-in process may be suitable for most IC devices, high-performance IC devices such as CMOS microprocessors that utilize a large amount of dynamic logic may not function properly at this type of high-temperature, high-voltage insitu burn-in conditions. If the dynamic logic within these IC devices is modified to withstand such insitu burn-in conditions, the size/performance of the dynamic logic would become quite uncompetitive.
Besides insitu burn-in tests, other types of burn-in tests may also be utilized. For example, if the IC device under test is not powered during the entire test interval, it is referred to as a static burn-in test. If the IC device under test is in some type of operation during the entire test interval, but the output from the operation is not monitored, it is then referred to as a dynamic burn-in test. Although either the static or dynamic burn-in test can be utilized as a substitute for the insitu burn-in test, there is no assurance that the internal node activities required for a successful burn-in test are actually occurring. Thus, the quality of the burn-in test may be suspect if the traditional standard insitu burn-in condition is not employed.
Here lies the dilemma. On one hand, IC devices having dynamic logic cannot be made to be robust enough to survive through a standard insitu burn-in test or the IC devices will become too large and too slow to remain competitive. On the other hand, a less harsh burn-in condition such as a static or a dynamic burn-in test cannot provide the required assurance and guarantee for the quality and reliability of the outgoing product. Consequently, it would be desirable to provide an improved method for performing a burn-in test on IC devices such that a different burn-in condition may be applied without sacrificing the integrity of the burn-in test as intended.